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[RAM control logic schematic]
RAM Control Logic.
U13 and U25 are multiplexers. The address output from the microprocessor are passed to RAM via U13 and U25 when the output Address Enable Control (AEC) from the VIC IC is "high". When AEC is "low" the VIC IC outputs refresh addresses on pins 24 - 31. AEC goes "low" when the system clock, phase 2, is "low". Since all I/O decoding occurs when phase 2 is "high", refresh is transparent to the processor.

Eight 4164 DRAMS provide 64k bytes of memory. One 2114 RAM (U6) provides 512 bytes of memory allocated for screen color data storage.

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This page has been created by Sami Rautiainen.
Last updated February 11, 1998.